1. Field of the Invention
The present invention relates generally to apparatus for accessing stored information and, more specifically, to a redundant memory circuit and a method of programming the circuit.
2. Discussion of Background and Prior Art
A wide variety of apparatus exists for accessing stored information. One type of apparatus is known as a redundant memory circuit, which has a memory for storing the information and circuitry for accessing the stored information. The memory, such as a programmable read-only memory (PROM) or a random access memory (RAM), generally has an array of programmable data bit storage elements arranged in a matrix of interconnected rows and columns. The circuitry used to access the information stored on the memory includes row and column address decoders which receive and decode row and column addresses and, thereby, activate the corresponding rows and columns. In, for example, a PROM, each programmable data bit storage element is a fuse which is programmed or "blown," i.e., opened, to store a data bit of one logic level, e.g., logic 1, or left closed to store a data bit of the other logic level, e.g. logic 0. The redundant memory circuit can be manufactured, for example, as an integrated circuit (IC) on a semiconductor chip and housed in an IC package.
In the manufacture of the memory, any one or more well-known defects can occur which cause a given bit or bits in a given row to be unusable for storing the information. Consequently, the redundant memory circuit typically is manufactured with the memory having a redundant row to replace the defective row and a programmable row address decoder which is used to access the redundant row in response to the address to the defective row. A general algorithm for making use of the redundant memory circuit involves two basic operations, which are first to deselect the defective row and then secondly to select the redundant row.
U.S. Pat. No. 4,250,570 to Tsang et al., issued Feb. 10, 1981, discloses such a redundant memory circuit. Two embodiments are described for deselecting a defective row. One of the two embodiments permanently physically deselects the defective row from its associated row address decoder, while the other embodiment electronically deselects the defective row from its row address decoder whenever the defective row is addressed. Tsang et al. also disclose an embodiment for selecting the redundant row.
In the one embodiment of the patent for physically deselecting a defective row, additional circuitry is provided between each row address decoder and the corresponding row of the memory. This additional circuitry includes a programmable fuse and other components, external of the memory, for coupling the output of the particular row address decoder to the corresponding row. After a defective row in the memory is identified, the corresponding row address decoder is enabled to pass programming current through the fuse and the other components, thereby opening the fuse and physically disconnecting the defective row from its row address decoder.
A problem with the one embodiment for physically deselecting the defective row is the fact that the additional circuitry is required between each row address decoder and the associated row in the memory, which has disadvantages such as the need for increased space on the IC chip to support this circuitry and higher manufacturing costs. Also, in the course of programming the memory to store the data bits, a good or non-defective row can be undesirably deselected. This can occur as a result of the programming current that is developed in the good row to store the bits causing current to flow through and open the external programmable fuse and, thereby, physically disconnect the good row from the corresponding row address decoder. Furthermore, while the defective row is physically disconnected from the corresponding row address decoder, internally of the memory the entire defective row, particularly the unprogrammed or closed data bit storage elements, is not disconnected from all the columns of the memory matrix. This means that the defective row will have parasitic capacitance that is coupled to the columns. Therefore, upon reading a good row, the parasitic capacitance tied to the columns that are also interconnected with the defective row still must be discharged, thereby disadvantageously reducing the speed of the memory access.
In the other embodiment of Tsang et al. for electronically deselecting a defective row, a redundant row address decoder, in particular a NAND gate, responds to the address to the defective row by outputting a signal to access the associated redundant row. In addition, this output signal is coupled through an inverter to disable all the other row address decoders associated with their corresponding rows, one of which is the row address decoder that also receives the address to the defective row. Thus, all the rows including the defective row, but not the redundant row, are electronically deselected when the address to the defective row is received by the redundant row address decoder. One disadvantage with this embodiment is that a delay is introduced in accessing the data stored in the redundant row, thereby reducing memory access speed. This is because a significant amount of time is needed to fully and reliably disable the other row address decoders before access should be made to the redundant row. Furthermore, as with the one embodiment mentioned above, the entire defective row is not disconnected internally from the columns, thereby resulting in the same disadvantage of reduced memory access speed upon reading a good row.
In the embodiment of Tsang et al. for selecting the redundant row, the redundant row address decoder is programmed to decode or respond to the address of the defective row to access the redundant row. An address buffer and associated decoder fuses of the decoder are associated with each bit of the defective row address. Essentially, the programming of the redundant row address decoder occurs bit-by-bit, in which all the address buffers except the address buffer corresponding to the bit currently being programmed are held at a high voltage level. Programming current is then passed through or sunk by the one address buffer to program one of the associated decoder fuse. The remaining decoder fuses associated with the remaining address buffers are programmed in the same manner with all the address buffers except one being held at the high voltage level at any one time during the programming.
A disadvantage with the prior programming of the redundant row address decoder is that at any given time all but one of the address buffers must be at a high voltage level. This presents a significant multiplexing problem in that a multiplexer must simultaneously switch very high input voltages to all of the address buffers but the one, and this is difficult to accomplish. This multiplexing of the high input voltages also complicates the method of programming the redundant row address decoder.
Furthermore, the programming current for the decoder fuses of the redundant row address decoder is not supplied in a controlled manner. That is, the programming current develops or increases through each decoder fuse until the fuse opens slightly. This has the disadvantage that the fuse may not open sufficiently from a programming point of view so as to provide a wide gap which reliably represents the bit of the row address. Still furthermore, the redundant row address decoder of the patent uses multiple emitter transistors (METs) whose output is coupled to the redundant row, which METs inherently have a low base to emitter voltage breakdown. Consequently, during the programming phase of the redundant row address decoder, the redundant row can be undesirably subjected to the programming voltages through this emitter-base voltage breakdown phenomenon, the consequence of which is that the programming voltage must be set at a lower limit than is optimum.
Another overall disadvantage of prior redundant memory circuits is that programming pads on the IC chip through which the programming currents are supplied, in addition to the other typical bonding pads, such as those through which the row and column addresses are supplied, are required in order to deselect a defective row and select the redundant row, thereby undesirably increasing the number of components needed for the circuit. Also, the programming of the prior redundant memory circuits typically occurs at a point in the manufacturing process known as the "wafer sort". When performed at this stage, the programming current must pass through long needle-like probes which have an undesirable resistive and inductive effect that limits the programming voltage and induces inductive voltage overshoots and ringing when a decoder fuse opens, thus potentially stressing the chip.